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PRELIMINARY
256Mb: x32 SDRAM
SYNCHRONOUS DRAM
FEATURES
* PC100 functionality * Fully synchronous; all signals registered on positive edge of system clock * Internal pipelined operation; column address can be changed every clock cycle * Internal banks for hiding row access/precharge * Programmable burst lengths: 1, 2, 4, 8, or full page * Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes * Self Refresh Mode * 64ms, 4,096-cycle refresh (15.6s/row) * LVTTL-compatible inputs and outputs * Single +3.3V 0.3V power supply * Supports CAS latency of 1, 2, and 3
MT48LC8M32B2 - 2 Meg x 32 x 4 banks
For the latest data sheet, please refer to the Micron Web site: www.micron.com/sdramds
Pin Assignment (Top View) 86-Pin TSOP
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 WE# CAS# RAS# CS# A11 BA0 BA1 A10 A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
OPTIONS
* Configuration 8 Meg x 32 (2 Meg x 32 x 4 banks)
MARKING
8M32B2 TG P F5 1 B5 1
* Package 86-pin TSOP (400 mil) 86-pin TSOP (400 mil) Lead-free 90-ball FBGA (8mm x 13mm) 90-ball FBGA (8mm x 13mm) Lead-free * Timing (Cycle Time) 6ns (166 MHz) 7ns (143 MHz) * Operating Temperature Range Commercial (0 to +70C) Industrial (-40C to +85C)
NOTE: 1. Available on -7 only
Part Number Example:
-6 -7 None IT 1
MT48LC8M32B2TG-7
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
Note: The # symbol indicates signal is active LOW.
KEY TIMING PARAMETERS
SPEED GRADE -6 -7 CLOCK ACCESS TIME FREQUENCY CL = 3* 166 MHz 143 MHz 5.5ns 6.0ns SETUP TIME 1.5ns 2ns HOLD TIME 1ns 1ns
8 Meg x 32 Configuration Refresh Count Row Addressing Bank Addressing Column Addressing 2 Meg x 32 x 4 banks 4K 4K (A0-A11) 4 (BA0, BA1) 512 (A0-A8)
*CL = CAS (READ) latency
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
256Mb: x32 SDRAM
90-Ball FBGA Assignment (Top View)
1 A
DQ26
2
3
4
5
6
7
8
9
DQ24
VSS
VDD
DQ23
DQ21
B
DQ28 VDDQ VSSQ VDDQ VSSQ DQ19
C
VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ
D
VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ
E
VDDQ DQ31 NC NC DQ16 VSSQ
F
VSS DQM3 A3 A2 DQM2 VDD
G
A4 A5 A6 A10 A0 A1
H
A7 A8 NC NC BA1 A11
J
CLK CKE A9 BA0 CS# RAS#
K
DQM1 NC NC CAS# WE# DQM0
L
VDDQ DQ8 VSS VDD DQ7 VSSQ
M
VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ
N
VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ
P
DQ11 VDDQ VSSQ VDDQ VSSQ DQ4
R
DQ13 DQ15 VSS VDD DQ0 DQ2
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32 SDRAM
256Mb (x32) SDRAM PART NUMBER
PART NUMBER MT48LC8M32B2TG ARCHITECTURE 8 Meg x 32
GENERAL DESCRIPTION
The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, highspeed, random-access operation. The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
TABLE OF CONTENTS
Functional Block Diagram - 8 Meg x 32 ................. Pin Descriptions ........................................................... Functional Description .......................................... Initialization ........................................................... Register Definition ................................................. Mode Register ................................................... Burst Length ................................................ Burst Type .................................................... CAS Latency ................................................ Operating Mode ......................................... Write Burst Mode ....................................... Commands .................................................................. Truth Table 1 (Commands and DQM Operation) ........... Command Inhibit ................................................. No Operation (NOP) ............................................ Load Mode Register ............................................... Active ....................................................................... Read ....................................................................... Write ....................................................................... Precharge ................................................................. Auto Precharge ....................................................... Burst Terminate ...................................................... Auto Refresh ........................................................... Self Refresh .............................................................. Operation .................................................................... Bank/Row Activation ........................................... Reads ....................................................................... Writes ....................................................................... Precharge ................................................................. Power-Down .......................................................... Clock Suspend ........................................................ Burst Read/Single Write ........................................ Concurrent Auto Precharge ................................. Write With Auto Precharge ................................. 5 6 9 9 9 9 9 10 11 11 11 12 12 13 13 13 13 13 13 13 13 14 14 14 15 15 16 22 24 24 25 25 26 27 28 29 31 Absolute Maximum Ratings ...................................... 33 DC Electrical Characteristics and Operating Conditions ......................................... 33 IDD Specifications and Conditions ........................... 33 Capacitance .................................................................. 34 AC Electrical Characteristics (Timing Table) ..... 34 AC Functional Characteristics ............................ 35 Timing Waveforms Initialize and Load Mode Register ...................... Power-Down Mode ............................................... Clock Suspend Mode ............................................ Auto Refresh Mode ............................................... Self Refresh Mode .................................................. Reads Read - Single Read ........................................... Read - Without Auto Precharge ................... Read - With Auto Precharge .......................... Alternating Bank Read Accesses ..................... Read - Full-Page Burst ..................................... Read - DQM Operation ................................. Writes Write - Single Write ......................................... Write - Without Auto Precharge .................. Write - With Auto Precharge ........................ Alternating Bank Write Accesses ................... Write - Full-Page Burst .................................... Write - DQM Operation ................................ Package 86-Pin TSOP ...................................................... 90-Ball FBGA .................................................... 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Truth Table 2 (CKE) ..................................................... Truth Table 3 (Current State, Same Bank) ...................... Truth Table 4 (Current State, Different Bank) .................
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PRELIMINARY
256Mb: x32 SDRAM
FUNCTIONAL BLOCK DIAGRAM 8 Meg x 32 SDRAM
CKE CLK CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 BANK0
COMMAND DECODE
MODE REGISTER
REFRESH 12 COUNTER
12 12
ROWADDRESS MUX
12
BANK0 ROWADDRESS LATCH & DECODER
4096
BANK0 MEMORY ARRAY (4,096 x 512 x 32)
4
4
DQM0- DQM3
SENSE AMPLIFIERS 32
4,096
DATA OUTPUT REGISTER
2
A0-A11, BA0, BA1
14
ADDRESS REGISTER
2
BANK CONTROL LOGIC
I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 32 512 (x32) DATA INPUT REGISTER
32
DQ0- DQ31
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH
9
89
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
PIN DESCRIPTIONS
PIN NUMBERS 68 SYMBOL TYPE CLK Input DESCRIPTION Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWERDOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: WE# , CAS#, and RAS# (along with CS#) define the command being entered. Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) during a READ cycle. DQM0 corresponds to DQ0-DQ7, DQM1 corresponds to DQ8-DQ15, DQM2 corresponds to DQ16-DQ23 and DQM3 corresponds to DQ24-DQ31. DQM0-DQM3 are considered same state when referenced as DQM. Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: A0-A11 are sampled during the ACTIVE command (row-address A0-A10) and READ/WRITE command (column-address A0-A8 with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 [HIGH]) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command.
67
CKE
Input
20
CS#
Input
17, 18, 19
WE#, CAS#, RAS# DQM0- DQM3
Input
16, 71, 28, 59
Input
22, 23
BA0, BA1 Input
25-27, 60-66, 24, 21
A0-A11
Input
2, 74, 85, 40,
4, 5, 7, 8, 10, 11, 13, 76, 77, 79, 80, 82, 83, 31, 33, 34, 36, 37, 39, 42, 45, 47, 48, 50, 51, 53, 54, 56
DQ0- DQ31
Input/ Data I/Os: Data bus. Output
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
PIN DESCRIPTIONS (continued)
PIN NUMBERS 14, 30, 57, 69, 70, 73 3, 9, 35, 41, 49, 55, 75, 81 6, 12, 32, 38, 46, 52, 78, 84 1, 15, 29, 43 44, 58, 72, 86 SYMBOL TYPE NC - VDDQ VSSQ VDD VSS Supply Supply Supply Supply DESCRIPTION No Connect: These pins should be left unconnected. Pin 70 is reserved for SSTL reference voltage supply. DQ Power Supply: Isolated on the die for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Power Supply: +3.3V 0.3V. Ground.
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
BALL DESCRIPTIONS
90-BALL FBGA
J1
SYMBOL
CLK
TYPE
Input
DESCRIPTION
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (twoclock latency) when during a READ cycle. DQM0 corresponds to DQ0-DQ7, DQM1 corresponds to DQ8-DQ15, DQM2 corresponds to DQ16-DQ23 and DQM3 corresponds to DQ24-DQ31. DQM0-3 are considered same state when referenced as DQM. Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command Address Inputs: A0-A11 are sampled during the ACTIVE command (rowaddress A0-A11) and READ/WRITE command (column-address A0-A8; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data Input/Output: Data bus
J2
CKE
Input
J8
CS#
Input
J9, K7, K8 K9, K1, F8, F2
RAS#, CAS# WE# DQM0-3
Input Input
J7, H8
BA0, BA1
Input
G8, G9, F7, F3, G1, G2, G3, H1, H2, J3, G7, H9
A0-A11
Input
R8, N7, R9, N8, P9, M8, M7, L8, L2, M3, M2, P1, N2, R1, N3, R2, E8, D7, D8, B9, C8, A9, C7, A8, A2, C3, A1, C2, B1, D2, D3, E2 E3, E7, H3, H7, K2, K3 B2, B7, C9, D9, E1, L1, M9, N9, P2, P7 B8, B3, C1, D1, E9, L9, M1, N1, P3, P8 A7, F9, L7, R7 A3, F1, L3, R3
DQ0-DQ31
I/O
NC VDDQ VSSQ VDD VSS
- Supply Supply Supply Supply
No Connect: These pins should be left unconnected. H3 is a not connect for this part but may be used as A12 in future designs. DQ Power: Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Power Supply: Voltage dependant on option. Ground.
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
FUNCTIONAL DESCRIPTION
In general, this 256Mb SDRAM (2 Meg x 32 x 4 banks) is a quad-bank DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32-bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A11 select the row). The address bits (A0-A8) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
REGISTER DEFINITION
Mode Register The Mode Register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 1. The Mode Register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode Register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10, M11, BA0, and BA1 are reserved for future use. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a fullpage burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A8 when the burst length is set to two; by A2-A8 when the burst length is set to four; and by A3- A8 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100s delay prior to issuing any command other than a COMMAND INHIBIT or a NOP. Starting at some point during this 100s period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100s delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in an unknown state, it should be loaded prior to applying any operational command.
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.
Table 1 Burst Definition
Burst Length Starting Column Address A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported
2
Figure 1 Mode Register Definition
4
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
11
10
9
8
7
6
5
4 BT
3
2
1
0
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency
Burst length
*Should program M10, M11, BA0, BA1 = "0" to ensure compatibility with future devices.
8
Burst Length M2 M1 M0 000 001 010 011 100 101 110 111 M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 1 2 4 8 Reserved Reserved Reserved Reserved
Full Page (256)
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 n = A0-A8 Cn + 3, Cn + 4... ...Cn - 1, (Location 0 -256) Cn...
NOTE:
M3 0 1 Burst Type Sequential Interleave
M6 M5 M4 000 001 010 011 100 101 110 111
CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved
1. For a burst length of two, A1-A8 select the blockof-two burst; A0 selects the starting column within the block. 2. For a burst length of four, A2-A8 select the blockof-four burst; A0-A1 select the starting column within the block. 3. For a burst length of eight, A3-A8 select the blockof-eight burst; A0-A2 select the starting column within the block. 4. For a full-page burst, the full row is selected and A0-A8 select the starting column. 5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. For a burst length of one, A0-A8 select the unique column to be accessed, and mode register bit M3 is ignored.
M8 0 -
M7 0 -
M6 - M0 Defined -
Operating Mode Standard operation All other states reserved
M9 0 1
Write Burst Mode Programmed Burst Length Single Location Access
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
Figure 2 CAS Latency
T0 CLK COMMAND T1 T2
Table 2 CAS Latency
ALLOWABLE OPERATING FREQUENCY (MHz) SPEED -6 -7 CAS LATENCY = 1 50 50 CAS LATENCY = 2 100 100 CAS LATENCY = 3 166 143
READ tLZ
NOP tOH DOUT
DQ tAC CAS Latency = 1
T0 CLK COMMAND
T1
T2
T3
READ
NOP tLZ
NOP tOH DOUT
DQ tAC CAS Latency = 2
T0 CLK COMMAND
T1
T2
T3
T4
READ
NOP
NOP tLZ
NOP tOH DOUT
DQ tAC CAS Latency = 3
DON'T CARE UNDEFINED
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
COMMANDS
Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following the Operation section; these tables provide current state/next state information.
TRUTH TABLE 1 - COMMANDS AND DQM OPERATION
(Note: 1) NAME (FUNCTION) COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z NOTE: 1. 2. 3. 4. CS# RAS# CAS# WE# DQM H L L L L L L L L - - X H L H H H L L L - - X H H L L H H L L - - X H H H L L L H L - - X X X L/H 8 L/H 8 X X X X L H ADDR X X Bank/Row Bank/Col Bank/Col X Code X Op-Code - - DQs X X X X Valid Active X X X Active High-Z 5 6, 7 2 8 8 3 4 4 NOTES
5. 6. 7. 8.
CKE is HIGH for all commands shown except SELF REFRESH. A0-A11 define the op-code written to the Mode Register. A0-A11 provide row address, BA0 and BA1 determine which bank is made active. A0-A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0 and BA1 determine which bank is being read from or written to. A10 LOW: BA0 and BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0 and BA1 are "Don't Care." This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls DQ0-DQ7; DQM1 controls DQ8-DQ15; DQM2 controls DQ16-DQ23; and DQM3 controls DQ24-DQ31.
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COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The mode register is loaded via inputs A0-A11. See mode register heading in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0 and BA1 (B1) inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQMx signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQMx signal was registered LOW, the corresponding DQs will provide valid data. DQM0 corresponds to DQ0-DQ7, DQM1 corresponds to DQ8-DQ15, DQM2 corresponds to DQ16- DQ23 and DQM3 corresponds to DQ24-DQ31. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A0-A8 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. AUTO PRECHARGE Auto precharge is a feature which performs the same individual-bank PRECHARGE function described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet.
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BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analagous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The 256Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (tREF), regardless of width option. Providing a distributed AUTO REFRESH command every 15.625s will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms. SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become "Don't Care" with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting SELF REFRESH mode, AUTO REFRESH commands must be issued every 15.625ms or less as both SELF REFRESH and AUTO REFRESH utililze the row refresh counter.
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OPERATION
BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. See Figure 3. After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be issued. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 4, which covers any case where 2 < tRCD (MIN)/tCK - 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by t RRD.
Figure 3 Activating a Specific Row in a Specific Bank
CLK CKE CS# HIGH
RAS#
CAS#
WE#
A0-A11
ROW ADDRESS
BA0, BA1
BANK ADDRESS
Example: Meeting
T0 CLK
tRCD
Figure 4 (MIN) When 2 < tRCD (MIN)/tCK - 3
T1 T2 T3
tCK COMMAND ACTIVE NOP tRCD (MIN)
tCK NOP
tCK READ or WRITE
tRCD (MIN) +0.5 tCK tRCD (MIN) = 20ns, tCK = 8ns tRCD (MIN) x tCK where x = number of clocks for equation to be true.
DON'T CARE
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READs READ bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 6 shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixedlength READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 7 for CAS latencies of one, two and three; data
Figure 5 READ Command
CLK CKE CS# HIGH
T0 CLK COMMAND
Figure 6 CAS Latency
T1 T2
READ tLZ
NOP tOH DOUT
DQ tAC CAS Latency = 1
RAS#
T0
T1
T2
T3
CAS#
CLK COMMAND
WE#
READ
NOP tLZ
NOP tOH DOUT
DQ
A0-A7 A8, A9, A11
COLUMN ADDRESS
tAC CAS Latency = 2
ENABLE AUTO PRECHARGE
T0 CLK
T1
T2
T3
T4
A10
DISABLE AUTO PRECHARGE
COMMAND
READ
NOP
NOP tLZ
NOP tOH DOUT
BA0,1
BANK ADDRESS
DQ
tAC CAS Latency = 3 DON'T CARE UNDEFINED
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element n + 3 is either the last of a burst of four or the last desired of a longer burst. This 256Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 8, or each subsequent READ may be performed to a different bank.
Figure 7 Consecutive READ Bursts
T0 CLK T1 T2 T3 T4 T5
COMMAND
READ
NOP
NOP
NOP
READ X = 0 cycles
NOP
ADDRESS
BANK, COL n
BANK, COL b
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b
CAS Latency = 1
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
X = 1 cycle
ADDRESS
BANK, COL n
BANK, COL b
DQ
CAS Latency = 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b
T0 CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
X = 2 cycles
ADDRESS
BANK, COL n
BANK, COL b
DQ
CAS Latency = 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b
NOTE: Each READ command may be to either bank. DQM is LOW. DON'T CARE
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Figure 8 Random READ Accesses
T0 CLK T1 T2 T3 T4
COMMAND
READ
READ
READ
READ
NOP
ADDRESS
BANK, COL n
BANK, COL a
BANK, COL x
BANK, COL m
DQ
CAS Latency = 1
DOUT n
DOUT a
DOUT x
DOUT m
T0 CLK
T1
T2
T3
T4
T5
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL a
BANK, COL x
BANK, COL m
DQ
CAS Latency = 2
DOUT n
DOUT a
DOUT x
DOUT m
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL a
BANK, COL x
BANK, COL m
DQ
CAS Latency = 3
DOUT n
DOUT a
DOUT x
DOUT m
NOTE: Each READ command may be to either bank. DQM is LOW. DON'T CARE
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Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixedlength READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention, as shown in Figures 9 and 10. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal; provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was low during T4 in Figure 10, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 10 shows the case where the additional NOP is needed.
Figure 9 READ to WRITE
T0 CLK DQM T1 T2 T3 T4
COMMAND ADDRESS
READ
NOP
NOP
NOP
WRITE
BANK, COL n
BANK, COL b
Figure 10 READ to WRITE with Extra Clock Cycle
T0 CLK T1 T2 T3 T4 T5
tCK tHZ DQ
DOUT n DIN b
tDS DON'T CARE NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required.
DQM
COMMAND ADDRESS
READ
NOP
NOP
NOP
NOP
WRITE
BANK, COL n
BANK, COL b
tHZ DQ
DOUT n DIN b
tDS
DON'T CARE NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank.
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A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 11 for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same
Figure 11 READ to PRECHARGE
T0 CLK
t RP
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
PRECHARGE X = 0 cycles
NOP
NOP
ACTIVE
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
DQ
CAS Latency = 1
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
T0 CLK
T1
T2
T3
T4
T5
T6
T7
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE X = 1 cycle
NOP
NOP
ACTIVE
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
DQ
CAS Latency = 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
T0 CLK
T1
T2
T3
T4
T5
T6
T7
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
DQ
CAS Latency = 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
NOTE: DQM is LOW.
DON'T CARE
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operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 12 for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst.
Figure 12 Terminating a READ Burst
T0 CLK T1 T2 T3 T4 T5 T6
COMMAND
READ
NOP
NOP
NOP
BURST TERMINATE X = 0 cycles
NOP
NOP
ADDRESS
BANK, COL n
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
CAS Latency = 1
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
NOP
NOP
NOP
BURST TERMINATE X = 1 cycle
NOP
NOP
ADDRESS
BANK, COL n
DQ
CAS Latency = 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
T0 CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
BURST TERMINATE
NOP
NOP
NOP
X = 2 cycles
ADDRESS
BANK, COL n
DQ
CAS Latency = 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
NOTE: DQM is LOW.
DON'T CARE
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 13. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations,auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 14). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixedlength WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 15. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. This 256Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 16, or each subsequent WRITE may be performed to a different bank.
Figure 14 WRITE Burst
T0 CLK T1 T2 T3
COMMAND
WRITE
NOP
NOP
NOP
Figure 13 WRITE Command
CLK CKE HIGH CS#
ADDRESS
BANK, COL n
DQ
DIN n
DIN n+1
Figure 15 WRITE to WRITE
T0 T1 T2 CLK
RAS#
CAS#
WE#
COMMAND
WRITE
NOP
WRITE
A0-A7 A8, A9, A11
COLUMN ADDRESS
ADDRESS
BANK, COL n
BANK, COL b
DQ
ENABLE AUTO PRECHARGE
DIN n
DIN n+1
DIN b
A10
DISABLE AUTO PRECHARGE
TRANSITIONING DATA
DON'T CARE
BA0,1
BANK ADDRESS
NOTE: DQM is LOW. Each WRITE command may be to any bank.
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Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixedlength WRITE burst may be immediately followed by a READ command. Once the READ command is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in Figure 17. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The "two-clock" write-back requires at least one clock plus time, regardless of frequency, in auto precharge mode. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 18. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The precharge will actually begin coincident with the clock-edge (T2 in Figure 18) on a "one-clock" tWR and sometime between the first and second clock on a "two-clock" tWR (between T2 and T3 in Figure 18.) In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Figure 16 Random WRITE Cycles
T0 CLK T1 T2 T3
Figure 18 WRITE to PRECHARGE
T0 CLK T1 T2 T3 T4 T5 T6
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK, COL n
BANK, COL a
BANK, COL x
BANK, COL m
tWR = 1 CLK (tCK > tWR)
DQM
DQ
DIN n
DIN a
DIN x
DIN m
t RP
COMMAND
WRITE
NOP
PRECHARGE
NOP
NOP
ACTIVE
NOP
DON'T CARE
ADDRESS
BANK a, COL n
t WR
BANK (a or all)
BANK a, ROW
DQ
DIN n
DIN n+1
Figure 17 WRITE to READ
T0 CLK T1 T2 T3 T4 T5
tWR = 2 CLK (when tWR > tCK)
DQM
t RP
COMMAND
WRITE
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK a, COL n
t WR
BANK (a or all)
BANK a, ROW
ADDRESS
BANK, COL n
BANK, COL b
DQ
DIN n
DIN n+1
DQ
DIN n
DIN n+1
DOUT b
DOUT b+1
NOTE:
DQM could remain LOW in this example if the WRITE burst is a fixed length of two. DON'T CARE
TRANSITIONING DATA
DON'T CARE
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Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 19, where data n is the last desired data element of a longer burst. PRECHARGE The PRECHARGE command (Figure 20) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0 and BA1 select the bank. When all banks are to be precharged, inputs BA0 and BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. POWER-DOWN Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress (see Figure 21). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS).
Figure 19 Terminating a WRITE Burst
T0 CLK T1 T2
COMMAND
WRITE
BURST TERMINATE
NEXT COMMAND
ADDRESS
BANK, COL n
(ADDRESS)
DQ
DIN n
(DATA)
NOTE: DQMs are LOW.
Figure 20 PRECHARGE Command
CLK CKE CS# HIGH
Figure 21 Power-Down
CLK tCKS CKE
(( )) (( ))
> tCKS
(( ))
RAS#
COMMAND
NOP
(( )) (( ))
NOP
ACTIVE
All banks idle
CAS#
Input buffers gated off Enter power-down mode. Exit power-down mode.
tRCD tRAS tRC DON'T CARE
WE#
A0-A9, A11
All Banks
A10
Bank Selected
BA0,1
BANK ADDRESS
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CLOCK SUSPEND The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, "freezing" the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figures 22 and 23.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the Mode Register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0).
Figure 22 CLOCK SUSPEND During WRITE Burst
T0 CLK T1 T2 T3 T4 T5
Figure 23 CLOCK SUSPEND During READ Burst
T0 CLK T1 T2 T3 T4 T5 T6
CKE
CKE
INTERNAL CLOCK
INTERNAL CLOCK
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
NOP
WRITE
NOP
NOP
ADDRESS
BANK, COL n
ADDRESS
BANK, COL n
DQ
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DIN
DIN n
DIN n+1
DIN n+2
DON'T CARE
DON'T CARE
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and DQM is LOW.
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CONCURRENT AUTO PRECHARGE An access command to (READ or WRITE) another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. Micron SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. READ with auto precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24). 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).
Figure 24 READ With Auto Precharge Interrupted by a READ
T0 CLK
READ - AP BANK n READ - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
READ with Burst of 4
Interrupt Burst, Precharge t RP - BANK n
Idle tRP - BANK m Precharge
Internal States
BANK m
Page Active
READ with Burst of 4
ADDRESS DQ
BANK n, COL a
BANK m, COL d DOUT a DOUT a+1 DOUT d DOUT d+1
CAS Latency = 3 (BANK n) CAS Latency = 3 (BANK m)
NOTE: DQM is LOW.
Figure 25 READ With Auto Precharge Interrupted by a WRITE
T0 CLK
READ - AP BANK n Page Active WRITE - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
READ with Burst of 4
Interrupt Burst, Precharge tRP - BANK n
Idle t WR - BANK m Write-Back
Internal States
BANK m
BANK n, COL a
Page Active
WRITE with Burst of 4
ADDRESS 1 DQM DQ
BANK m, COL d
DOUT a CAS Latency = 3 (BANK n)
DIN d
DIN d+1
DIN d+2
DIN d+3
NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4. DON'T CARE
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WRITE WITH AUTO PRECHARGE 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26). 4. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (Figure 27).
Figure 26 WRITE With Auto Precharge Interrupted by a READ
T0 CLK
WRITE - AP BANK n READ - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back tWR - BANK n
Precharge tRP - BANK n tRP - BANK m
Internal States
BANK m
Page Active
READ with Burst of 4
ADDRESS DQ
BANK n, COL a DIN a DIN a+1
BANK m, COL d DOUT d CAS Latency = 3 (BANK m) DOUT d+1
NOTE: 1. DQM is LOW.
Figure 27 WRITE With Auto Precharge Interrupted by a WRITE
T0 CLK
WRITE - AP BANK n WRITE - AP BANK m
T1
T2
T3
T4
T5
T6
T7
COMMAND BANK n
NOP
NOP
NOP
NOP
NOP
NOP
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back tWR - BANK n
Precharge tRP - BANK n t WR - BANK m Write-Back
Internal States
BANK m
Page Active
WRITE with Burst of 4
ADDRESS DQ NOTE: 1. DQM is LOW.
BANK n, COL a DIN a DIN a+1 DIN a+2
BANK m, COL d DIN d DIN d+1 DIN d+2 DIN d+3
DON'T CARE
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TRUTH TABLE 2 - CKE
(Notes: 1-4) CKE n-1 CKE n L L CURRENT STATE Power-Down Self Refresh Clock Suspend L H Power-Down Self Refresh Clock Suspend H L All Banks Idle All Banks Idle Reading or Writing H NOTE: 1. 2. 3. 4. 5. H COMMAND n X X X COMMAND INHIBIT or NOP COMMAND INHIBIT or NOP X COMMAND INHIBIT or NOP AUTO REFRESH VALID See Truth Table 3 ACTION n Maintain Power-Down Maintain Self Refresh Maintain Clock Suspend Exit Power-Down Exit Self Refresh Exit Clock Suspend Power-Down Entry Self Refresh Entry Clock Suspend Entry 5 6 7 NOTES
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state of the SDRAM immediately prior to clock edge n. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. All states and sequences not shown are illegal or reserved. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1.
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TRUTH TABLE 3 - CURRENT STATE BANK n, COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page) CURRENT STATE Any CS# RAS# CAS# WE# H L L Idle L L L L Row Active Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) NOTE: L L L L L L L L L L X H L L L L H H L H H L H H H L H X H H L L H L L H L L H H L L H H X H H H L L H L L H L L L H L L L COMMAND (ACTION) COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) ACTIVE (Select and activate row) AUTO REFRESH LOAD MODE REGISTER PRECHARGE READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Deactivate row in bank or banks) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Truncate READ burst, start PRECHARGE) BURST TERMINATE READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE (Truncate WRITE burst, start PRECHARGE) BURST TERMINATE 7 7 11 10 10 8 10 10 8 9 10 10 8 9 NOTES
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/ accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
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NOTE (continued):
Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. All states and sequences not shown are illegal or reserved. Not bank-specific; requires that all banks are idle. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. Does not affect the state of the bank and acts as a NOP to that bank. Write w/Auto Precharge Enabled:
5.
6. 7. 8. 9. 10. 11.
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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TRUTH TABLE 4 - CURRENT STATE BANK n, COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page) CURRENT STATE Any Idle Row Activating, Active, or Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) Read (With Auto Precharge) Write (With Auto Precharge) CS# RAS# CAS# WE# H L X L L L L L L L L L L L L L L L L L L L L NOTE: X H X L H H L L H H L L H H L L H H L L H H L X H X H L L H H L L H H L L H H L L H H L L H X H X H H L L H H L L H H L L H H L L H H L L COMMAND (ACTION) COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) Any Command Otherwise Allowed to Bank m ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE 7, 8, 16 7, 8, 17 9 7, 8, 14 7, 8, 15 9 7, 12 7, 13 9 7, 10 7, 11 9 7 7 NOTES
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/ accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
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NOTE (continued):
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m's burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 7). 11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24). 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25). 16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26). 17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 27).
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ABOLUTE MAXIMUM RATINGS
*Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD, VDDQ Supply Relative to VSS .............................................. -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS .............................................. -1V to +4.6V Operating Temperature, TA ............................ 0C to +70C Storage Temperature (plastic) ............ -55C to +150C Power Dissipation ........................................................ 1W Operating Temperature, TA (IT) ........... -40C to +85C
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 6; notes appear on page 36) (VDD, VDDQ = +3.3V 0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Any input 0V VIN VDD (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V VOUT VDDQ OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) SYMBOL VDD, VDDQ VIH VIL II IOZ VOH VOL MIN 3 2 -0.3 -5 -5 2.4 - MAX 3.6 VDDQ+ 0.3 0.8 5 5 - 0.4 UNITS NOTES V V V A A V V 22 22
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CAPACITANCE
(Note: 2) PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs SYMBOL CI1 CI2 CIO MIN 2.5 2.5 4.0 MAX 4.0 4.0 6.5 UNITS pF pF pF
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 5, 6, 8, 9, 11; notes appear on page 36)
AC CHARACTERISTICS PARAMETER Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time -6 CL = 3 CL = 2 CL = 1 SYMBOL tAC (3) tAC (2) tAC (1) t AH t AS tCH tCL tCK (3) tCK (2) tCK (1) tCKH tCKS tCMH tCMS t DH t DS tHZ (3) tHZ (2) tHZ (1) tLZ tOH tRAS tRC tRFC tRCD tREF t RP tRRD tT tWR MIN MAX 5.5 7.5 17 MIN -7 MAX 6 8 17 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns tCK ns ns NOTES
CL = 3 CL = 2 CL = 1
CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time CL = 3 CL = 2 CL = 1 Data-out low-impedance time Data-out hold time ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period AUTO REFRESH period ACTIVE to READ or WRITE delay Refresh period (4,096 rows) PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time
1 1.5 2.5 2.5 6 10 20 1 1.5 1 1.5 1 1.5 5.5 7.5 17 1 2 42 60 60 18 18 12 0.3 1CLK+ 6ns 12ns 70
1 2 2.75 2.75 7 10 20 1 2 1 2 1 2 6 8 17 1 2.5 42 70 70 20 20 14 0.3 1CLK+ 7ns 14ns 70
23 23 23
10 10 10
120K
120K
64
64
1.2
1.2
25 7 24 27 20
Exit SELF REFRESH to ACTIVE command
tXSR
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AC FUNCTIONAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 36)
PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command SYMBOL tCCD tCKED t PED t DQD tDQM t DQZ t DWD tDAL (3) tDAL (2) tDAL (1) tDPL tBDL tCDL tRDL tMRD tROH (3) tROH (2) tROH (1) -6 1 1 1 0 0 2 0 5 4 3 2 1 1 2 2 3 2 1 -7 1 1 1 0 0 2 0 5 4 3 2 1 1 2 2 3 2 1 UNITS tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK NOTES 17 14 14 17 17 17 17 15, 21 15, 21 15, 21 16, 21 17 17 16, 21 26 17 17 17
CL = 3 CL = 2 CL = 1
Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command CL = 3 CL = 2 CL = 1
IDD SPECIFICATIONS AND CONDITIONS
(Notes: 1, 6, 11, 13; notes appear on page 36) (VDD, VDDQ = +3.3V 0.3V)
MAX PARAMETER/CONDITION SYMBOL -6 210 -7 190 UNITS mA NOTES 3, 18, 19, 26
IDD1 Operating Current: Active Mode; Burst = 2; READ or WRITE; t RC = tRC (MIN) Standby Current: Power-Down Mode; All banks idle; CKE IDD2N = LOW Standby Current: Power-Down Mode; All banks idle; CKE IDD2NS = HIGH Standby Current: Active Mode; CKE = HIGH; CS# = HIGH; IDD3NS All banks active after tRCD met; No accesses in progress IDD3N Standby Current: Active Mode; CKE = LOW; CS# = HIGH; All banks active; No accesses in progress IDD4 Operating Current: Burst Mode; Continuous burst; READ or WRITE; All banks active, half DQs toggling every cycle. tRFC = tRFC IDD5 Auto Refresh Current CKE = HIGH; CS# = HIGH (MIN) tRFC = IDD6 15.625s SELF REFRESH current: CKE < 0.2V
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
300 30 40 30 165 335 3 1
300 30 40 30 145 295 3 1
A mA mA mA mA mA mA mA 3, 18, 19, 26 3, 12, 18, 19, 26 3, 12, 19, 26
IDD7
35
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PRELIMINARY
256Mb: x32 SDRAM
NOTES
1. 2. All voltages referenced to VSS. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25C; pin under test biased at 1.4V. AC can range from 0pF to 6pF. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. Enables on-chip refresh and address counters. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C T A +70C and -40C TA +85C for IT parts) is ensured. An initial pause of 100s is required after powerup, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. AC characteristics assume tT = 1ns. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 12. Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 143 MHz for -7, 166 MHz for -6. 22. VIH overshoot: VIH (MAX) = VDDQ + 1.2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -1.2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. 23. The clock frequency must remain constant during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. 25. JEDEC and PC100 specify three clocks. 26. tCK = 7ns for -7, 6ns for -6. 27. Check factory for availability of specially screened devices having tWR = 10ns. tWR = 1 tCK for 100 MHz and slower ( tCK = 10ns and higher) in manual precharge.
3.
4. 5.
6.
7. 8.
Q 30pF
9. Outputs measured at 1.5V with equivalent load: 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD tests have VIL = .25 and VIH = 2.75, with timing referenced to 1.5V crossover point.
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
36
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PRELIMINARY
256Mb: x32 SDRAM
INITIALIZE AND LOAD MODE REGISTER
T0 CLK (( ))
(( )) (( ))
tCK
T1
tCKS
tCKH
(( )) (( )) (( )) (( ))
Tn + 1 tCH
(( )) (( ))
To + 1 tCL
(( )) (( ))
Tp + 1
Tp + 2
Tp + 3
CKE
(( )) tCMS tCMH
AUTO REFRESH
(( )) NOP NOP (( )) (( )) (( ))
(( ))
tCMS tCMH COMMAND
(( )) (( ))
tCMS tCMH
(( )) PRECHARGE (( ))
NOP
AUTO REFRESH
(( )) NOP NOP (( )) (( )) (( ))
LOAD MODE REGISTER
NOP
ACTIVE
DQM 0-3
(( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
A0-A9, A11
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( ))
tAS
tAH
ROW
CODE
ALL BANKS SINGLE BANK
tAS
tAH
ROW
A10
CODE
BA0, BA1
ALL BANKS
(( )) (( ))
BANK
DQ
(( )) T = 100s (MIN) Power-up: VDD and CK stable
High-Z
(( )) tRP tRFC tRFC tMRD
Precharge all banks
AUTO REFRESH
AUTO REFRESH
Program Mode Register 1, 2 DON'T CARE UNDEFINED
NOTE: 1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired. 2. Outputs are guaranteed High-Z after command is issued.
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
POWER-DOWN MODE1
T0 CLK tCK T1 tCL tCKS CKE tCKS tCKH tCH T2
(( )) (( ))
Tn + 1
Tn + 2
tCKS
(( ))
tCMS tCMH COMMAND
PRECHARGE NOP NOP
(( )) (( )) (( )) (( )) (( )) (( ))
NOP
ACTIVE
DQM 0-3
A0-A9, A11
ALL BANKS
ROW
A10
SINGLE BANK
(( )) (( ))
ROW
tAS BA0, BA1
tAH
(( )) (( ))
(( ))
BANK(S)
BANK
High-Z
DQ Two clock cycles Precharge all active banks All banks idle, enter power-down mode
Input buffers gated off while in power-down mode All banks idle Exit power-down mode DON'T CARE UNDEFINED
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
CLOCK SUSPEND MODE1
T0 CLK tCK T1 tCL tCH tCKS tCKH CKE tCKS tCKH T2 T3 T4 T5 T6 T7 T8 T9
tCMS tCMH COMMAND
READ NOP NOP NOP NOP NOP WRITE NOP
tCMS tCMH DQM0-3 tAS A0-A9, A11 tAH
COLUMN e 2
COLUMN m 2
tAS A10 tAS BA0, BA1
tAH
tAH
BANK BANK
tAC DQ tLZ
DOUT m
tAC tOH
tHZ
DOUT m + 1
tDS
tDH
DOUT e + 1
DOUT e
DON'T CARE UNDEFINED
NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled. 2. A9 and A11 = "Don't Care."
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
AUTO REFRESH MODE
T0
CLK tCK
T1
T2
tCH
(( )) (( ))
(( ))
Tn + 1
tCL
(( )) (( ))
(( ))
To + 1
CKE tCKS tCMS COMMAND tCKH tCMH
NOP AUTO REFRESH NOP
PRECHARGE
(( )) ( ( NOP )) (( )) (( ))
(( )) (( ))
AUTO REFRESH
NOP
(( )) ( ( NOP )) (( )) (( ))
(( )) (( )) (( )) (( ))
ACTIVE
DQM 0-3
A0-A9, A11
ALL BANKS
ROW
A10
SINGLE BANK
(( )) (( ))
ROW
tAS
tAH
BA0, BA1
BANK(S)
(( )) (( ))
(( )) tRP tRFC tRFC
(( )) (( ))
(( ))
BANK
DQ
High-Z
Precharge all active banks
DON'T CARE
UNDEFINED DON'T CARE
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
SELF REFRESH MODE
T0 CLK tCK T1 tCH tCL T2
(( )) (( ))
Tn + 1
tCKS
> tRAS
(( )) (( )) (( )) (( ))
To + 1
To + 2
CKE tCKS tCMS COMMAND tCKH tCMH
NOP AUTO REFRESH
(( ))
tCKS
PRECHARGE
(( )) (( )) (( )) (( )) (( )) (( ))
NOP ( (
(( ))
AUTO REFRESH
))
DQM 0-3
(( )) (( )) (( )) (( )) (( )) (( ))
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
(( )) (( ))
t AS BA0, BA1
tAH
(( )) (( )) (( )) (( ))
BANK(S)
DQ
High-Z tRP Precharge all active banks Enter self refresh mode
(( ))
(( ))
tXSR Exit self refresh mode (Restart refresh time base)
DON'T CARE UNDEFINED
CLK stable prior to exiting self refresh mode
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
SINGLE READ - WITHOUT AUTO PRECHARGE1
T0 CLK tCKS CKE tCMS COMMAND tCMH NOP tCMS DQM / DQML, DQMH tAS A0-A9, A11 tAS A10 tAS BA0, BA1 tAH ROW tAH ROW tAH BANK DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK COLUMN m2 ROW READ tCMH PRECHARGE NOP ACTIVE tCKH tCK T1 tCL tCH T2 T3 T4 T5
ACTIVE
ALL BANKS ROW
tAC DQ tRCD tRAS tRC CAS Latency tRP tLZ
tOH
DOUTm
tHZ
DON'T CARE
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. A9 and A11 = "Don't Care."
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
READ - WITHOUT AUTO PRECHARGE1
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP READ NOP NOP NOP PRECHARGE NOP ACTIVE
T1 tCK tCKH tCL
T2 tCH
T3
T4
T5
T6
T7
T8
ACTIVE
tCMS DQM 0-3 tAS A0-A9, A11 tAS A10 tAS BA0, BA1 tAH
ROW
tCMH
COLUMN m 2
ROW
tAH
ROW
ALL BANKS ROW DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK
tAH
BANK
tAC DQ tRCD tRAS tRC tLZ CAS Latency
tAC tOH
DOUT m
tAC tOH
DOUT m + 1
tAC tOH
DOUT m + 2
tOH
DOUT m + 3
tHZ tRP
DON'T CARE UNDEFINED
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. A9 and A11 = "Don't Care."
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
READ - WITH AUTO PRECHARGE1
T0 CLK tCKS CKE tCMS tCMH COMMAND
ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE
T1 tCK tCKH tCL
T2 tCH
T3
T4
T5
T6
T7
T8
tCMS DQM 0-3 tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m 2
ROW
tAS A10
tAH
ENABLE AUTO PRECHARGE ROW
ROW
tAS BA0, BA1
tAH
BANK BANK
BANK
tAC tAC DQ tRCD tRAS tRC tLZ CAS Latency tOH
DOUT m
tAC tOH
DOUT m + 1
tAC tOH
DOUT m + 2
tOH
DOUT m + 3
tHZ tRP
DON'T CARE UNDEFINED
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2. 2. A9 and A11 = "Don't Care."
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
ALTERNATING BANK READ ACCESSES1
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP READ NOP ACTIVE NOP READ NOP ACTIVE
T1 tCK tCKH tCL
T2 tCH
T3
T4
T5
T6
T7
T8
ACTIVE
tCMS DQM 0-3 tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m 2
ROW
COLUMN b 2
ROW
tAS A10
tAH
ENABLE AUTO PRECHARGE ROW
ENABLE AUTO PRECHARGE ROW
ROW
tAS BA0, BA1
tAH
BANK 0 BANK 4 BANK 4 BANK 0
BANK 0
tAC DQ tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRRD tLZ CAS Latency - BANK 0
tAC tOH
DOUT m
tAC tOH
DOUT m + 1
tAC tOH
DOUT m + 2
tAC tOH
DOUT m + 3
tAC tOH
DOUT b
tRP - BANK 0
tRCD - BANK 0
tRCD - BANK 4
CAS Latency - BANK 4
DON'T CARE UNDEFINED
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2. 2. A9 and A11 = "Don't Care."
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
READ - FULLL-PAGE BURST1
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP READ NOP NOP NOP NOP
T1 tCL tCH tCKH tCK
T2
T3
T4
T5
T6
(( )) (( ))
Tn + 1
Tn + 2
Tn + 3
Tn + 4
(( )) (( )) (( )) (( )) (( )) (( ))
ACTIVE
NOP
BURST TERM
NOP
NOP
tCMS DQM 0-3
tCMH
tAS A0-A9, A11
tAH
COLUMN m 2
ROW
(( )) (( ))
tAS A10
tAH
ROW
(( )) (( ))
tAS BA0, BA1
tAH
BANK
BANK
(( )) (( ))
tAC tAC DQ tLZ tRCD CAS Latency tOH
Dout m
tAC tOH
DOUT m+1
tAC ( ( )) tOH
(( )) DOUT m+2 (( ))
tAC tOH
DOUT m-1
tAC tOH
DOUT m
tOH
DOUT m+1
tHZ
256 locations within same row
Full page completed Full-page burst does not self-terminate. 3 Can use BURST TERMINATE command.
DON'T CARE UNDEFINED
NOTE: 1. For this example, the CAS latency = 2. 2. A9 and A11 = "Don't Care." 3. Page left open; no tRP.
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
READ - DQM OPERATION1
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP READ NOP NOP NOP NOP NOP NOP
T1 tCK tCKH tCL
T2 tCH
T3
T4
T5
T6
T7
T8
ACTIVE
tCMS DQM 0-3 tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m 2 ENABLE AUTO PRECHARGE
tAS A10
tAH
ROW
tAS BA0, BA1
tAH
BANK
DISABLE AUTO PRECHARGE BANK
tAC DQ tLZ tRCD CAS Latency
tOH
DOUT m
tAC
tAC tOH
DOUT m + 2
tOH
DOUT m + 3
tHZ
tLZ
tHZ
DON'T CARE UNDEFINED
NOTE: 1. For this example, the CAS latency = 2. 2. A9 and A11 = "Don't Care."
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PRELIMINARY
256Mb: x32 SDRAM
SINGLE WRITE
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP PRECHARGE NOP ACTIVE
tCK tCKH
T1
tCL
T2 tCH
T3
T4
T5
T6
ACTIVE
tCMS tCMH DQM / DQML, DQMH tAS A0-A9, A11 tAH
COLUMN m 3 ALL BANKS ROW DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK ROW
ROW
tAS A10
tAH
ROW
tAS BA0, BA1
tAH
BANK
tDS DQ tRCD tRAS tRC
tDH DIN m t WR 2 tRP
DON'T CARE
NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a "manual" PRECHARGE. 2. tWR is required between and the PRECHARGE command, regardless of frequency. 3. A9 and A11 = "Don't Care."
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
WRITE - WITHOUT AUTO PRECHARGE1
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP NOP NOP PRECHARGE NOP ACTIVE
tCK tCKH
T1
tCL
T2 tCH
T3
T4
T5
T6
T7
T8
ACTIVE
tCMS tCMH DQM 0-3 tAS A0-A9, A11 tAH
COLUMN m 3 ALL BANKs ROW DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK ROW
ROW
tAS A10
tAH
ROW
tAS BA0, BA1
tAH
BANK
tDS DQ tRCD tRAS tRC
tDH DIN m
tDS
tDH
tDS
tDH
tDS
tDH
DIN m + 1
DIN m + 2
DIN m + 3 t WR 2 tRP
DON T CARE
NOTE: 1. 2. 3. 4.
For this example, the burst length = 4, and the WRITE burst is followed by a "manual" PRECHARGE. Faster frequencies require two clocks (when tWR > tCK). A9 and A11 = "Don't Care." t WR of 1 CLK available if running 100 MHz or slower. Check factory for availability.
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
WRITE - WITH AUTO PRECHARGE1
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP NOP NOP NOP NOP NOP ACTIVE
tCK tCKH
T1
tCL
T2 tCH
T3
T4
T5
T6
T7
T8
T9
ACTIVE
tCMS tCMH DQM 0-3 tAS A0-A9, A11 tAH
COLUMN m 3 ENABLE AUTO PRECHARGE ROW ROW
ROW
tAS A10
tAH
ROW
tAS BA0, BA1
tAH
BANK BANK
BANK
tDS DQ tRCD tRAS tRC
tDH DIN m
tDS
tDH
tDS
tDH
tDS
tDH
DIN m + 1
DIN m + 2
DIN m + 3 tWR 2 tRP
DON'T CARE
NOTE: 1. For this example, the burst length = 4. 2. Faster frequencies require two clocks (when tWR > tCK). 3. A9 and A11 = "Don't Care."
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
ALTERNATING BANK WRITE ACCESSES1
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE
tCK tCKH
T1
tCL
T2 tCH
T3
T4
T5
T6
T7
T8
T9
ACTIVE
tCMS DQM 0-3 tAS A0-A9, A11 tAH
tCMH
ROW
COLUMN m 3
ROW
COLUMN b 3
ROW
tAS A10
tAH
ENABLE AUTO PRECHARGE ROW
ENABLE AUTO PRECHARGE ROW
ROW
tAS BA0, BA1
tAH
BANK 0 BANK 1 BANK 1 BANK 0
BANK 0
tDS DQ tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRRD
tDH DIN m
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH DIN b
tDS
tDH
tDS
tDH
tDS
tDH
DIN m + 1
DIN m + 2
DIN m + 3
DIN b + 1 tRP - BANK 0
DIN b + 2
DIN b + 3 tRCD - BANK 0
tWR2 - BANK 0
tRCD - BANK 4
tWR - BANK 4
DON'T CARE
NOTE: 1. For this example, the burst length = 4. 2. Faster frequencies require two clocks (when tWR > tCK). 3. A9 and A11 = "Don't Care."
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
WRITE - FULL-PAGE BURST
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP NOP NOP
T1 tCL tCH tCKH tCK
T2
T3
T4
T5
(( )) (( ))
Tn + 1
Tn + 2
Tn + 3
(( )) (( )) (( )) (( ))
ACTIVE
NOP
BURST TERM
NOP
tCMS tCMH DQM 0-3
(( )) (( ))
tAS A0-A9, A11
tAH
COLUMN m 1
ROW
(( )) (( ))
tAS A10
tAH
ROW
(( )) (( ))
tAS BA0, BA1
tAH
BANK
BANK
(( )) (( ))
tDS DQ tRCD
tDH DIN m
tDS
tDH
tDS
tDH
tDS
tDH
DIN m + 1
DIN m + 2
DIN m + 3
(( )) (( ))
tDS
tDH
DIN m - 1
256 locations within same row
Full-page burst does not self-terminate. Can use BURST TERMINATE command to stop.2, 3
Full page completed
NOTE: 1. A9 and A11 = "Don't Care." 2. tWR must be satisfied prior to PRECHARGE command. 3. Page left open; no tRP.
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
WRITE - DQM OPERATION1
T0 CLK tCKS CKE tCMS COMMAND tCMH
NOP WRITE NOP NOP NOP NOP NOP
T1 tCK tCKH tCL
T2 tCH
T3
T4
T5
T6
T7
ACTIVE
tCMS tCMH DQM 0-3 tAS A0-A9, A11 tAH
COLUMN m 2 ENABLE AUTO PRECHARGE
ROW
tAS A10
tAH
ROW
tAS BA0, BA1
tAH
DISABLE AUTO PRECHARGE BANK
BANK
tDS DQ tRCD
tDH
DIN m
tDS
tDH
tDS
tDH
DIN m + 2
DIN m + 3
DON'T CARE
NOTE: 1. For this example, the burst length = 4. 2. A9 and A11 = "Don't Care."
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
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PRELIMINARY
256Mb: x32 SDRAM
86-PIN PLASTIC TSOP (400 MIL)
22.22 .08 .61 .50 TYP +.07 0.20 -.03 .10 (2X)
SEE DETAIL A
2.80 (2X) 11.76 .10 10.16 .08
R .75 (2X) PIN #1 ID R 1.00 (2X) +.03 .15 -.02 .25 GUAGE PLANE +.10 .10 -.05 .10 1.20 MAX .80 TYP DETAIL A .50 .10
NOTE:
1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
54
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.
PRELIMINARY
256Mb: x32 SDRAM
90-BALL FBGA (8mm x 13mm)
0.65 0.05
SEATING PLANE C
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3%Ag, 0.5% Cu SOLDER MASK DEFINED BALL PADS: O0.40
0.10 C
90X O0.45 0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS O0.42 BALL A9
6.40 0.80 TYP
SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC
BALL A1 ID
BALL A1 ID BALL A1
0.80 TYP 11.20 0.10 C L 13.00 0.10
5.60 0.05 6.50 0.05
C L 3.20 0.05 4.00 0.05 1.00 MAX
8.00 0.10
(Bottom View)
NOTE: 1. All dimensions in millimeters. 2. Recommended pad size for PCB is 0.33mm0.025mm. Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
09005aef80cd8e48 256MbSDRAMx32.p65 - Rev. B; Pub. 03/04
55
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.

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